MIPI Video Interfaces
Recently i had an opportunity to work with the much celebrated MIPI Video interfaces , specifically MIPI CSI-2 Interface.
CSI-2 is one among the various MIPI Alliance standards , all of them are proprietary. It is meant to interface High Speed/High Resolution Cameras to mobile processors like Snapdragon.
Unlike conventional video interfaces where pixel clock is the main reference time stamp, MIPI is little bit different.
To start with understanding, consider MIPI as just a data transfer protocol like UART, but obviously not simple as UART.
The beauty of MIPI lies in two main factors.
1. Low Power Consumption
2. Scalable Speed.
The actual MIPI Specification talks about a lot of features that should/or may have for MIPI compatibility. But here we can concise the spec to few points like.
1. The actual video transmission is done in High Speed State, in Differential signalling
2. The interface goes to a low power state during the video blanking times(H/V).
3. The clock rate calculation for CSI is dependent on the method of implementation.
4. Clock Lane provides a DDR clock (half of data rate)
4. A very specific set of timings should be followed for SoT/EoT transitions.
CSI-2 is one among the various MIPI Alliance standards , all of them are proprietary. It is meant to interface High Speed/High Resolution Cameras to mobile processors like Snapdragon.
Unlike conventional video interfaces where pixel clock is the main reference time stamp, MIPI is little bit different.
To start with understanding, consider MIPI as just a data transfer protocol like UART, but obviously not simple as UART.
The beauty of MIPI lies in two main factors.
1. Low Power Consumption
2. Scalable Speed.
The actual MIPI Specification talks about a lot of features that should/or may have for MIPI compatibility. But here we can concise the spec to few points like.
1. The actual video transmission is done in High Speed State, in Differential signalling
2. The interface goes to a low power state during the video blanking times(H/V).
3. The clock rate calculation for CSI is dependent on the method of implementation.
4. Clock Lane provides a DDR clock (half of data rate)
4. A very specific set of timings should be followed for SoT/EoT transitions.
MIPI Clock rate calculation for
particular video standard depends on 4 parameters.
·
Resolution (720p, 1080p, 2160 p …. etc)
·
Frame rate (60/30/25/50…. fps…)
·
Video Format (YUV422, RG888, RAW12…etc)
·
Number of MIPI data lanes in use (1,2,4,…etc)
Example :- Consider
a 4 lane MIPI for transfer of 1080p60fps YUV422 video
Resolution =
2200*1125 total frame
Frame Rate = 60 fps
Hence Video's Pixel Clock = Resolution * Frame Rate
= 148.5 Mhz
Bytes per pixel =
2 bytes or 16 bits, since YUV422
So Total Bandwidth = 148.5 * 16
=
2376 Mbps
Per Lane Bandwidth = 2376/4
=
594Mbps
MIPI Clock (half rate) =
594/2
= 297 Mhz
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