Highspeed Serial I/O

Serialisation has become the order of data communication in these days. It seems like that parallel transfer is in oblivion. Nowadays, whatever new method of data transfer is introduced, it seems to work using various pairs of serial data lines in one or other form. Some of the best examples are USB, HDMI, Firewire (ieee 1394),PCIe, SATA, Ethernet, MIPI interfaces (DSI, CSI) etc..

During the old days it was considered parallel transfer could give more throughput. To some extent it was true. A parallel transfer could take a complete byte, word or quad word at a single clock to the receiving device, whereas a bit could only be transferd at a single clock edge in  a serial line. From old days itself serial transfer co-existed in form of USART, UART, SPI, I2C etc, but was limited to very small clock rates for small speed peripherals. By then, parallel method dominated for chip to chip and box transfers like ISA, SCSI, PCI, PATA IDE etc. But as clock rates increased , some problems with parallel transfer dominated. One major issue was to ensure the proper registering of parallel data bits concurrently from all paths. PCB tracks which carry the parallel bits needed to be exactly length matched for concurrent transfer of data. Even a fractional difference lead to path delays and hence issued wrong registering of bits. Another drawback of parallel interface was the simultaneous switching of different lines leading to wild power stability issues in data lines, current sinking differences.

So serialization gained popularity. Also, introduction of fractional phase detector took the serial data rates from Mhz to Ghz range. This lead to introduction to Multi Gigabit serial links which are prominent nowadays.

Yes, various parameters where modified in recent years ranging from line coding, physical signalling schemes, impedance matched tracks and proper on/off chip termination parameters.

Single Ended and Differential Ended Serial Lines

                    Single Ended lines are systems where a single signal connection is made between communicating devices.This incoming signal is compared with a specified voltage range (TTL, CMOS,  HSTL)  and reference ground. Here both the device should comply to work in same reference voltage family.

                  Differential signalling uses two connections per each signal line used. At the first thought it seems to be idiotic since two tracks are needed for a signal propagation. But at high speed serial links, this method is a boon and evolves as the most efficient one to meet power, area, time constraints.

These two lines are complementary to each other, ie the other line carries the negated value of original data being transmitted. So, for reception, the incoming signals are compared to each other for determining the actual data. So no reference level is employed here as in single ended method.

Thus, if the signal referenced as the positive node has a higher voltage than the one referenced negative, the signal is high, or one. If the negative referenced signal is more positive, the signal is low, or zero.

This method has several advantages over single-ended signaling. For example, it is much less susceptible to noise. It helps to maintain a constant current flow into the driving IC (receiver IC).

But as clock speeds become fast and processing time touched nanoseconds range, simple one channel serial communication was not enough. So there introduced the concept of mutiple serial pairs , or precisely more differential serial pairs. Its is simply using more differential pairs dedicated for particular data in the system.

A best example is PCIe

In PCIe, its various speed are specified by 4X, 8X, 16X etc:-

The numbers 4, 8, 16 refers to the number of serial differential lanes it uses to increase speed.

ie a PCIe 16X card has 16 lanes for data transfer(16 differential Tx pairs and 16 differential Rx pairs)  and hence it will be 16 times faster than a 1X PCIe card, which has only one lane for data transfer (1 differential Tx pair and 1 differential Rx pair).

[Actual bitrates are not discussed here for simplicity beacause PCIe has versions extending from 1.0 to 4.0. The base 1X speed of each version is different. for eg:- A PCIe ver1.0 1X gives a speed of 200Mbps in single direction.]

This made PCIe a best system to operate as a back plane BUS in High Performance Computing Systems. Hence the old 32-bit parallel PCI retired from the scene and PCIe become the de-facto in back planes.

We all know that nothing is enough for all time.. The need for much higher bandwidth kept on increasing and transfer delays and jitter allowance become more stringent. The need for high speed systems in day today life also become common. An example is the intrusion of true HD video systems which need to transfer huge amount of data to display TV panels. So inter connectivity become more challenging.  But still Serial I/O provides the best cost effective method for both on/off chip communications.

An overview is presented above about serial I/O , there exists huge inner actions for the successful synchronization of a very high speed Serial link. Such techniques include various line encoding schemes, Clock Data Recovery circuits, DC balancing in differential pairs (transition minimizing techniques  ), serialise-deserialise processes, etc:- . I would like to talk about it later from an FPGA design scenario. SERDES or GTX blocks are little magicians who do these trick.

 But lets conclude this here...