Real Time Clock IP Core
A completely synthesizeable IP core of a Real Time Clock (RTC) is presented here. Specifications 1. Alarm Set capability 2. AM/PM notification 3. Last Alarm time memory Info HDL used : VHDL Tested on an Altera DE2 FPGA deveopment board.see the screenshots. Download link to source VHDL files http://www.mediafire.com/?ud1bt4zl05y5v6s Bugs are always tricky.. so download, try , and report back if any exists.. But i am sure u will love to explore the code because.. it will teach u abt reading hardware pins, using it in digital logic.. driving 'LED 7 segments' and interacting with the design using push buttons and slide switches etc....